Low Temperature CMOS IC Design (LTICDesign)
CMOS IC low temperature operation is devised as a promising technique to control leakage current and therefore total IC power given its exponential dependence with temperature. Ioff reduction at lower temperature comes from the increase of the MOSFET threshold voltage when the device is cooled down, thus compensating for the nominal (high temperature) reduced Vt. It is well known that carrier’s mobility is higher at lower temperatures resulting in increased saturation current and thus better device driving capability in the low temperature regime.
Low temperature operation also benefits interconnect behavior, since aluminum and copper resistivity decrease when temperature is lowered. The reduction in wiring resistance improves circuit performance and electromigration bounds as maximum current density can be higher.
Cooling techniques are expected to achieve better efficiency for practical applications. Once this step is achieved, MOS device and circuit design techniques for low temperature need careful consideration to exploit the advantages of this technology.
Delay and power depend on two type of parameters: device geometry's and circuit activity. Once the gate layout is known, the delay and the power can be determined as a function of activity. We develop a model that computes delay (including noise due to x-tk), power, and finally a thermal map
- Delay
The gate delay model accounts for: 1) The non-linear dependence of delay with fan-out, input transition time, or temperature, 2) the gate delay dependence with the specific switching input for multi-input gates, and 3) Geometric parameters of the MOS transistors in the gate.
- Power
Power estimation accounts for the dynamic component including shortcircuit, and leakage in complex multi-input gates.
- Temperature increase with respect to ambient temperature due to self-heating
Once power and delay are known, the thermal map is computed:
Not a full list
J.L. Rosselló and J. Segura
IEE Electronic Letters, Vol. 41, No. 3, pp. 122-124, February 2005
A technique to accurately estimate the leakage power in CMOS nanometre integrated circuits (ICs) is presented. The model has similar accuracy to SPICE and represents an important improvement with respect to previous works. The model can be used for a fast and accurate estimation of the standby power dissipated by large circuits.
Sebastià A. Bota, Josep L. Rosselló, C. De Benito, Ali Keshavarzi, and Jaume Segura
IEEE Desing & Test of Computers, Vol. 23, No. 5, pp. 414-424, Sept.-Oct. 2006.
Trends in CMOS IC scaling are leading to nanometer VLSI circuits with increasing power dissipation and operating temperatures. The effect of increasing circuit junction temperature on delay, together with reliability concerns, challenges thermal management in high-performance ICs. This article analyzes the impact of thermal-map temperature changes on clock delay and discusses differences between buffered and nonbuffered trees.
S. Bota, M. Rosales, J.L. Rossello, A. Keshavarzi, J. Segura
IEEE Int. Test Conference, pp. 1276-1283, Oct. 2004
As chips become faster, the need to test them at their intended speed of operation has been recognized. High-speed operation, together with the higher switching activity typically induced during test, can result in a die-thermal distribution significantly different from that achieved during normal operation. Differences in thermal map distribution between normal- and test-mode operations give rise to a non-uniform impact on the relative path delay within logic blocks. The impact of test-induced hot spots may artificially slow down non-critical paths or speed-up critical ones with respect to the clock making the whole die to fail (pass) delay testing for a good (bad) part. The non-uniform thermal-induced delay is especially important for clock circuitry, the most critical block, which is impacted even if exact zero-skew clock routing algorithms are adopted. In this work we analyze the impact of thermal map temperature changes on the clock delay identifying a new delay-fault mechanism. We propose a technique to minimize the impact of different test- and normal-mode thermal maps by making the clock tree speed independent of temperature gradients. This technique allows applying confidently delay test patterns to the die regardless of the thermal-map test-induced modification
J.L. Rosselló, V. Canals, S.A. Bota, A. Keshavarzi and J. Segura
Design Automation and Test in Europe (DATE'05)
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12mm technology showing excellent results.
S.A. Bota, M. Rosales, J. L. Rosselló, J. Segura
Design Automation and Test in Europe (DATE'05)
In this paper we present a simple and efficient built-in temperature sensor for thermal monitoring of standard-cell based VLSI circuits. The proposed smart temperature sensor uses a ring-oscillator composed of complex gates instead of inverters to optimize their linearity. Simulation results from a 0.18-_m CMOS technology show that the non-linearity error of the sensor can be reduced when an adequate set of standard logic gates is selected.
J. Rosselló, S. Bota, M. Rosales, A. Keshavarzi and J. Segura
THERMINIC'05
The ever-aggressive increase in performance and integration of CMOS ICs is leading to higher power dissipation and power density, with a consequent increase of the circuit junction temperature together with the generation of non-uniform thermal maps and hot-spots. Moreover, it has been predicted that technology scaling willbring static power to a significant fraction of the total
power, complicating further this analysis due to the exponential dependence of leakage with temperature. This scenario represents an important challenge in circuit design due to the lack of accurate and compact thermal models capable of describing not only the impact of non-uniform
thermal maps on circuit performance, but also on static leakage for an accurate power modeling. In this paper we analyze the influence of considering the leakage power contribution to the circuit thermal map and therefore on its overall power dissipation and performance. Based on the analysis of two key thermal parameters (the mean and the maximum junction temperatures) we derive design guidelines to reduce the impact of hot-spots on circuit performance and reliability using an entropy-based cost function for thermal optimization.
J. Rosselló, S. Bota and J. Segura
PATMOS, pp. 348-54, 2005
We present a compact model to estimate quickly and accurately the leakage power in CMOS nanometer Integrated Circuits (ICs). The model has similar accuracy than SPICE and represents an important improvement with respect to previous works. It has been developed to be used for fast and accurate estimation and optimization of the standby power dissipated by large cir-cuits