X. Gili, S. Barcelo, S. Bota and J. Segura
IEEE Trans. on Nuclear Science, Vol. 59, No. 4, pp. 971-979, 2012

We present a Single Event Transient (SET) propagation model that can be used to quantify the propagation likelihood of a given noise waveform trough CMOS logic gates. This analysis is key to predict if a SET induced within a combinational block is capable of causing a SEU. The model predicts the output noise characteristics given the input noise waveform for each gate, and can be applied to any CMOS technology through a one-time library parameter extraction process. Pulse propagation is described through continuous analytical functions that convert a SET pulse height and width at the gate input to a SET pulse height and width at its output. The noise transfer curves have relatively simple analytical continuous expressions suitable for an easy adoption within CAD tools, thus allowing the investigation of pulse propagation through an entire logic block. Comparison between simulations and model show a very good agreement for a commercial 65 nm technology.

G. Torrens, B. Alorda, S. Bota and J. Segura
IEEE Int. Reliability Physics Symposium, Montreal, 2009

We analyze two complementary radiation-hardening techniques for 6T SRAM memories compatible with structured layouts. One is based in selecting individually the Vt of each transistors in the cross-coupled inverters of the SRAM cell. The other is based in modifying the widths of all pmos or all nmos transistors of the cell. The first technique does not affect the cell layout and, therefore, is compatible with structured layouts. The second one increases the minimum width of all pmos by a factor kp and the minimum width of all nmos by a factor kn. This prevents using diffusion bends, and allows structured layouts. Both techniques provide SEU robustness improvement.

G. Torrens, B. Alorda, S. Barceló, J. Rosselló, S. Bota and J. Segura
IEEE Trans. on Circuits and Systems II, Vol. 57, No. 4, April 2010.

Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in turn, get worsened with technology scaling. We analyze two design alternatives to improve cell hardening compatible with regular cell layouts providing an extensive analysis to illustrate the benefits of each technique. One of the proposed solutions is based on transistor width modulation that provides an immunity enhancement at the cost of a moderate cell size increase. The other solution is based on multi-Vt selection showing a moderate immunity improvement at the cost of no impact on cell area. The combination of both techniques is shown to be optimum when considering other design metrics like SNM, read/write stability, access time and leakage. Results are demonstrated on 90 nm and 65 nm commercial technologies.

G. Torrens, S. Bota, J. Verd, B. Alorda, J. Merino, and J. Segura
Microtechnologies in the New millenium, SPIE 2009.

Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions even at ground level. To face this challenge, a designer must dispose of a variety of mitigation schemes adapted to their specific design constraints. Built In Current Sensors have been proposed as a detection scheme for single event upsets in SRAM. In this paper, Power-Bus current transients in SRAM memories for Single Event Upset Detection have been analyzed in a 65nm CMOS technology. The different types of current roles which are applied during the simulation is discussed. The results show the important contribution of leakage currents in the response of the memory cell to an external event.

Sebastià Bota, Gabriel Torrens, Bartomeu Alorda and Jaume Segura
IEEE Int. On-Line Testing Symposium, 2009

We analyze the effects of radiation-induced transient pulses on 6T SRAM cells operating in read mode. The critical charge of a memory cell during read mode is lower than in hold mode. For 1 to 0 upsets, this reduction reaches a factor ×1.5 for events produced by alpha particles; this factor is even higher for longer induced current pulses. The impact of events propagated through the bit-lines is also analyzed. Results show that it is possible the occurrence of an upset in the Sense Amplifier producing a wrong output in the readout process without changing the memory cell stored value.

S. A. Bota, J.L. Merino, B. Alorda, J. Verd, G. Torrens and J. Segura
European Radiation Effects on Components and Systems Conference, RADECS 2009

We present the design and operation of a monitor circuit that captures the effect of ionizing particles on sensitive CMOS IC internal nodes. The circuit implements a Single Event Effects (SEE) detector and a quick sampling block that captures the SEE induced waveform shape currents during a certain time window. These values can be read externally through a dedicated decoding circuitry. The circuit has been designed and fabricated on a 130nm technology. Preliminary experimental results and
detailed simulations are provided to demonstrate the feasibility of the system implemented.

B. Alorda, G. Torrens, S. Bota, J. Segura
Design Automation and Test in Europe, DATE 2010.

The main contribution of this work is providing a static and dynamic enhancement of bit-cell stability for low-power SRAMs in nanometer technologies. We consider a wide layout topology without bends in diffusion layers for the nanometer SRAM cell design to minimize the impact of process variations. The design restrictions imposed by such a nanometer SRAM cell design prevents from applying traditional read SNM improvement techniques. We use the SNM as a measure of the cell stability during read operations, and Qcrit to quantify the robustness against SEE during hold mode. The techniques proposed have a low impact on read time and leakage current while improving significantly the SNM. Moreover, such a technique has no impact on strategic cell parameters like area and leakage when in hold mode. Results obtained from both a commercial 65nm CMOS technology and a 45nm BPTM technology are provided.

B. Alorda, G. Torrens, S. Bota, J. Segura.
Microelectronics Reliability, Vol 51, No. 2, February 2011.

We analyze and compare the impact of radiation-induced transient effects based on evaluating the critical charge parameter for 6T and 8T SRAMs during hold, read and write operations. Results on a commercial 65nm CMOS technology show that 6T and 8T cells offer quite similar robustness when they are in hold. However, the critical charge observed in other operation modes is reduced a 55% respect to the hold operation. For this reason, we provide a thorough analysis of the critical charge behavior in 6T and 8T SRAMs to determine the dependence of memory radiationrobustness with memory state. Single Event Upsets and Single Event Transients have been considered in the analysis, showing that 8T have better performance than 6T. The dependence of critical charge with memory state for high workload memories modifies the overall memory SER estimation indicating the significance of analyzing the memory robustness as a memory state function. In general, the SER estimation results show that the robustness behavior of 8T-based cells is better than robustness behavior of 6T-based cells.

S. Barcelo, X. Gili, S. Bota, J. Segura
Design Automation and Test in Europe, DATE 2011

We present a STA tool based on a single-pass true path computation that efficiently determines the critical path list. Given that it does not rely on a two-step process it can be programmed to find efficiently the N true paths from a circuit. We also report and analyze the dependence of complex gates delay with the sensitization vector and its variation (that gets up to 15% in 65nm technologies), and consider such effect in the path delay estimation. Delay is computed from a simple polynomial analytical description that requires a one-time library parameter extraction process, making it highly scalable. Results on combinational ISCAS synthesized for three technologies (130nm, 90nm and 65nm) provide better results in computation time, number of paths reported and delay estimation for these paths compared to a commercial tool.

B. Alorda, G. Torrens, S. Bota and J. Segura
Design Automation and Test in Europe, DATE 2011

SRAM cell stability analysis is typically based on Static Noise Margin (SNM) evaluation when in hold mode, although memory errors may also occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM during read operations analyzing several alternatives to improve cell stability when in this mode. The techniques studied are based on transistor width, and word- and bit-line voltage modulations. We show that it is possible to improve cell stability during read operations while reducing current leakage, as opposed to present methods that improve cell read stability at the cost of leakage increase

S. Barcelo, X. Gili, S. Bota and J. Segura
IEEE Trans. on Very Large Scale Integration (VLSI) Systems. Vol. 22, No. 7, Jul. 2014

We report and analyze the dependence of complex gates delay with the sensitization vector and its variation -that gets up to 40% in 65-nm CMOS technologies- and include its effect in the path delay estimation -that can be in the order of 16%. The gate delay is computed from a simple polynomial analytical description that requires a one-time library parameter extraction process, making it highly scalable. An STA tool based on a single-pass true path computation is used to determine the critical path list. Since it does not rely on a two-step process, it can be programmed to find efficiently the N true paths from a circuit. Results from various benchmark circuits synthesized for three commercial technologies (130, 90, and 65 nm) provide better results in number of paths reported and delay estimation for these paths compared to a commercial tool. The impact of delay variation with the sensitization vector for paths with complex gates reveals as a significant mechanism that must be considered as it is comparable to the impact of parameter variations or interconnect-induced delay.